High Level Software Cost Estimation

This report is dedicated to the processor characterization method and software cost estimation technique used in the Polis Codesign tool environment. The processor characterization method has been exercised by applying it to the ARM processor family. In particular, two processors, ARM7TDMI and ARM920T, have been examined. An improved method is proposed, which is supported and partially automated by two utility tools. The improved method is based on an iterative two-pass technique. The first pass involves processor characteristic extraction from generic software templates. The second pass improves the parameters from the first pass using a validation method. The results obtained during the exercise are presented and discussed. In particular the effect of instruction and data cache memory is addressed. The estimation technique used today is well suited for processors without cache, but processors with cache calls for new techniques. Introduction High-level software cost estimation is an attractive feature in a system design flow. This allows the designer to estimate software code size and performance in an early design phase. The approach to high-level software cost estimation that is available in the Polis codesign environment developed at UC Berkeley [2] is based on work done by K. Suzuki et. al. [1]. Under the assumption that the software program can be represented as a set of directed acyclic graphs (DAG), called S-graphs, the estimation is performed using macro modeling. A number of macros, representing different types of nodes that constitute the Sgraph, are collected in a set of template files. The template files are profiled for the processor that will be used, and size and time parameters for each individual macro is extracted. The profiling is only performed once, using an Instruction Set Simulator (ISS) or debugger for the processor in question. The macro parameters are collected in a parameter file, which is used to estimate the cost for any software program that runs on the processor. In this way there is no need for a designer to install and learn any simulators or debuggers to evaluate the software cost on different microprocessors. This amounts to a fast and convenient way to do design trade-off decisions between hardware, software, and functionality of an embedded system. The main objective of this project was to exercise and possibly improve the processor characterization methodology in Polis. The ARM processor family was selected as suitable microprocessors to perform the experiments on for several reasons. The ARM processors are widely used and has up until now not been available in the Polis environment. The ARM cores are a family of processors with different characteristics, which allows a wide range of different processor configurations to be analyzed without changing the experimental framework radically. The ARM processor comes with a Software Development Kit (SDK) that contains a set of tools in an open environment. EECS249 Project Report 2 A second objective was to study the effects that instruction and data cache has on software cost estimation and to possibly suggest solutions to the expected problems. Some previous work in this direction has been performed by Lajalo et. al. [3]. Processor Characterization Processor Characterization in Polis is based on the assumption that the software program is decomposed into communicating Codesign Finite State-Machines (CFSMs) that are executed upon request by a scheduler or operating system. The communication between CFSMs is asynchronous, and a signal enables a CFSM when it is received. The scheduler executes enabled CFSMs according to a scheduling policy. Each CFSM can be represented by a polar directed acyclic graph (DAG) called an S-graph. When the CFSM is executed, only one execution path is traversed in the S-graph from the Begin to the End node. The Sgraph is composed of a fixed set of node types. Each node type in an S-graph is represented by a macro, which is an atomic operation. A macro will eventually be executed as a sequence of instructions on a microprocessor. The idea is that if the code size and execution time for each macro can be estimated, so can the S-graph, and hence the CFSM. If the CFSMs are annotated with the estimated execution time, simulation of the system will yield a performance estimate of the whole system, this is referred to as performance simulation. The goal for processor characterization is thus to estimate the code size and execution time of the macros that constitute the S-graphs. All macro cost estimates are collected in a parameter file, which is processor specific. The parameter file is read by Polis, which annotates the software before performance simulation can be carried out. Estimating the macros involves compiling and analyzing the code for the intended processor. The current methodology for parameter file generation is outlined in Figure 1.